ADPLL (All-Digital Phase-Locked Loop) frequency synthesizers are conventionally available, which are provided with a digitally controlled oscillator (DCO) and use dithering by a ΔΣ modulator to improve frequency resolution. This type of ADPLL frequency synthesizer is disclosed, for example, in Patent Literature 1. FIG. 1 is a diagram showing a configuration of the conventional ADPLL frequency synthesizer disclosed in Patent Literature 1.
In FIG. 1, digitally controlled oscillator (DCO) 1 is made up of inductor element 2, negative resistance element 3, varactor array 4 and varactor array 5. Varactor array 4 and varactor array 5 each have a plurality of varactors. All the varactors have the same capacitance. The capacitance value of each varactor is controlled by binary control signals. The capacitance value of the varactor is controlled, and an oscillating frequency fCKV of DCO 1 is thereby controlled.
The oscillating frequency fCKV is expressed by equation 1 using a total capacitance value C of varactor array 4 and varactor array 5 and an inductance value L of inductor element 2.
                              (                      Equation            ⁢                                                  ⁢            1                    )                ⁢                                                                                                f          CKV                =                  1                      2            ⁢                                                  ⁢            π            ⁢                          LC                                                          [        1        ]            
To be more specific, the capacitance value of the varactor is controlled as follows. First, phase comparator 9 compares the phase of a reference signal FREF and the phase of an output CKV of DCO 1 and generates a phase error signal. Loop filter 11 then filters the phase error signal and outputs the filtered phase error signal as a DCO control signal TUNE_T. The TUNE_T signal is made up of an integer part and a fraction part. The integer part is inputted to tracking varactor control section 6 and the fraction part is inputted to tracking varactor control section 7.
Tracking varactor control section 6 converts the integer part to an OTW (Oscillator Tuning Word) integer signal and outputs this OTW integer signal to varactor array 4 and thereby adjusts the capacitance of varactor array 4. On the other hand, tracking varactor control section 7 converts the fraction part to an OTW fract signal and outputs the OTW fract signal to varactor array 5 and thereby adjusts the capacitance of varactor array 5. Tracking varactor control section 7 includes a ΔΣ (delta-sigma) modulator.
As described above, the conventional ADPLL frequency synthesizer constitutes a negative feedback system and performs PLL (Phase Locked Loop) operation.
By the way, tracking varactor control section 6 operates in synchronization with a CKR clock which is a signal resulting from returning the reference signal FREF with the CKV and tracking varactor control section 7 operates in synchronization with a CKVD clock which is a signal resulting from frequency-dividing the CKV using frequency divider 8. The CKVD frequency is set to be sufficiently larger than the CKR frequency. This allows the ΔΣ modulator of tracking varactor control section 7 to obtain a dithering effect and improves the frequency resolution of the CKV signal.